1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly, to a static random-access memory (referred to hereinafter as an SRAM) comprised of memory cells, the basic elements of which are flip-flops.
2. Description of the Related Art
In recent years, in the field of SRAMs, there has been active development in the area of devices which are configured with so-called high-load-resistance type memory cells or TFT (thin-film transistor) load type memory cells. In SRAMs of this type, as in other semiconductor memory devices, the achievement of a high level of integration requires that the memory cell surface area be made small, and to achieve this efforts are being made to shrink the size of the MOS transistors which make up the memory cells.
The need to achieve good reliability and low power consumption in these down-sized MOS transistors makes necessary memory cells that can operate stably at low voltages, and development of such memory cells is being actively pursued.
In memory cells of typical SRAMs in the past, the drive element is a pair of MOS transistors and corresponding load elements, which form a flip-flop, with an MOS transistor transfer gate transistor which responds to the word line potential connected between the input/output node of the flip-flop and a pair of complementary bit lines.
In this configuration, when the memory cell is selected, it is possible to read out data using a prior art method. In such cases, a current flows from one of the pair of complementary bit lines via the transfer gate transistor and drive transistor into the low-potential power supply line. When this happens, the potential at the connection point of the two transistors (one of the input/output nodes of the flip-flop) rises to a voltage level established by the gm (mutual conductance) of the transfer gate transistor and the gm of the drive transistor. As a result, the other drive transistor opposing this drive transistor goes into what is called a "weak` ON state, which causes the potential at the other input/output node of the flip-flop to drop.
In this type of operating mode, if both the proportion of drop in the potential of one of the input/output nodes of the flip-flop and the proportion of rise in the potential at the other input/output node are large, as described later, the data stored in this memory cell is inverted, thereby preventing the achievement of stable operation.
This problem becomes more pronounced at low operating voltages. While raising the operating voltage solves this problem, doing creates the another problem of increased power consumption.
To solve this problem, it is thought that the value of (MOS drive transistor drive ability)/(transfer gate transistor MOS transistor drive ability), that is, the ratio of the former to the latter (hereinafter referred to as the cell ratio) can be made large.
However, if this is done, the size of the MOS transistor for the drive element becomes large, resulting in relative increase in the surface area of the memory cell.
The problems involved with prior art will be described in detail later, in a comparison with preferred embodiments of the present invention.